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AMD’s Piledriver chips to use Cyclos’s resonant clock mesh

AMD to use Cyclos’s resonant clock mesh in its upcoming Piledriver successor in order to reduce the chip’s clock distribution power. By using on-chip inductors creating electric pendulum, also known as “Tank” circuits, will form large capacitance of the clock mesh in parallel with the inductors. In return the system recycles clock power rather than dissipating on every clock cycle as with traditional systems.

“Now that the Cyclos technology is validated, we’re looking forward to expand into SoC designs via the design automation tools that are in development at Cyclos. We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption,” said Papaefthymiou, founder and president of Cyclos.

Cyclos has not given much detail on the Piledriver core but did say it will be a “4+ Ghz” and fabbed on a 32nm process node. As for when we’ll start seeing this: “We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule.”, AMD’s Samuel Naffziger said.

(full understanding of the Cyclos’s technology can be found here)


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